CAV24C256WE-GT3 Datasheet, PDF (3/11 Pages) ON Semiconductor – 256-Kb I2C CMOS Serial EEPROM

CAV24C256
Table 5. A.C. CHARACTERISTICS (V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.) (Note 7)
Standard
Fast
Fast−Plus
Symbol
Parameter
Min
Max
Min
Max
Min
Max
F_SCL
Clock Frequency
100
400
1,000
t_HD:STA
START Condition Hold Time
4
0.6
0.25
t_LOW
Low Period of SCL Clock
4.7
1.3
0.45
t_HIGH
High Period of SCL Clock
4
0.6
0.40
t_SU:STA
START Condition Setup Time
4.7
0.6
0.25
t_HD:DAT
Data In Hold Time
0
0
0
t_SU:DAT
Data In Setup Time
250
100
50
t_R (Note 8)
SDA and SCL Rise Time
1,000
300
100
t_F (Note 8)
SDA and SCL Fall Time
300
300
100
t_SU:STO
STOP Condition Setup Time
4
0.6
0.25
t_BUF
Bus Free Time Between
4.7
1.3
0.5
STOP and START
t_AA
SCL Low to Data Out Valid
3.5
0.9
0.40
t_DH
Data Out Hold Time
50
50
50
T_i (Note 8)
Noise Pulse Filtered at SCL
50
50
50
and SDA Inputs
t_SU:WP
t_HD:WP
t_WR
t_PU
(Notes 8, 9)
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
0
2.5
5
1
0
2.5
5
1
0
1
5
0.1
1
7. Test conditions according to “A.C. Test Conditions” table.
8. Tested initially and after a design or process change that affects this parameter.
9. t_PU is the delay between the time V_CC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
0.2 x V_CC to 0.8 x V_CC
≤ 50 ns
Input Reference Levels
0.3 x V_CC, 0.7 x V_CC
Output Reference Levels
Output Load
0.5 x V_CC
Current Source: I_L = 3 mA; C_L = 100 pF
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
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