74HC138 Datasheet, PDF (5/9 Pages) NXP Semiconductors – 3-to-8 line decoder/demultiplexer; inverting

INPUT A
t_PLH
OUTPUT Y
74HC138
SWITCHING WAVEFORMS
VALID
50%
50%
VALID
t_PHL
t_r
V_CC
INPUT CS1
90%
50%
GND
10%
t_PHL
90%
50%
OUTPUT Y
10%
t_THL
Figure 1.
Figure 2.
t_f
V_CC
GND
t_PLH
t_TLH
INPUT
90%
50%
CS2, CS3 10%
OUTPUT Y
t_f
t_PHL
90%
50%
10%
t_THL
Figure 3.
t_r
t_PLH
V_CC
GND
t_TLH
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is selected,
determine which of the eight outputs is active−low.
CONTROL INPUTS
CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the
Address inputs. For any other combination of CS1, CS2, and
CS3, the outputs are at a logic high.
OUTPUTS
Y0 − Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
Active−low Decoded outputs. These outputs assume a
low level when addressed and the chip is selected. These
outputs remain high when not addressed or the chip is not
selected.
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