74HC138 Datasheet, PDF (4/9 Pages) NXP Semiconductors – 3-to-8 line decoder/demultiplexer; inverting

74HC138
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
V_IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V_out = 0.1 V or V_CC – 0.1 V
|I_out| v 20 mA
V_CC
Guaranteed Limit
(V) −55_C to 25_C v 85_C v 125_C Unit
2.0
1.5
3.0
2.1
4.5
3.15
6.0
4.2
1.5
1.5
V
2.1
2.1
3.15
3.15
4.2
4.2
V_IL Maximum Low−Level Input
V_out = 0.1 V or V_CC – 0.1 V
2.0
0.5
Voltage
|I_out| v 20 mA
3.0
0.9
4.5
1.35
6.0
1.8
0.5
0.5
V
0.9
0.9
1.35
1.35
1.8
1.8
V_OH Minimum High−Level Output V_in = V_IH or V_IL
Voltage
|I_out| v 20 mA
2.0
1.9
4.5
4.4
6.0
5.9
1.9
1.9
V
4.4
4.4
5.9
5.9
V_in = V_IH or V_IL |I_out| v 2.4 mA 3.0
|I_out| v 4.0 mA 4.5
|I_out| v 5.2 mA 6.0
V_OL Maximum Low−Level Output V_in = V_IH or V_IL
2.0
Voltage
|I_out| v 20 mA
4.5
6.0
2.48
3.98
5.48
0.1
0.1
0.1
2.34
2.20
3.84
3.70
5.34
5.20
0.1
0.1
V
0.1
0.1
0.1
0.1
I_in
Maximum Input Leakage
Current
V_in = V_IH or V_IL |I_out| v 2.4 mA 3.0
|I_out| v 4.0 mA 4.5
|I_out| v 5.2 mA 6.0
V_in = V_CC or GND
6.0
0.26
0.26
0.26
±0.1
0.33
0.40
0.33
0.40
0.33
0.40
±1.0
±1.0
mA
I_CC Maximum Quiescent Supply V_in = V_CC or GND
Current (per Package)
I_out = 0 mA
6.0
4
40
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Symbol
Parameter
Guaranteed Limit
V_CC
(V) −55_C to 25_C v 85_C v 125_C Unit
t_PLH,
t_PHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 4)
2.0
135
3.0
90
4.5
27
6.0
23
170
205
ns
125
165
34
41
29
35
t_PLH,
t_PHL
Maximum Propagation Delay, CS1 to Output Y
(Figures 2 and 4)
2.0
110
3.0
85
4.5
22
6.0
19
140
165
ns
100
125
28
33
24
28
t_PLH,
t_PHL
Maximum Propagation Delay, CS2 or CS3 to Output Y
(Figures 3 and 4)
2.0
120
3.0
90
4.5
24
6.0
20
150
180
ns
120
150
30
36
26
31
t_TLH,
t_THL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
C_in Maximum Input Capacitance
−
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Package)*
55
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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