MMBF4391LT1_06 Datasheet, PDF (4/6 Pages) ON Semiconductor – JFET Switching Transistors N-Channel

MMBF4391LT1, MMBF4392LT1, MMBF4393LT1
NOTE 1
R_GEN
50 W
V_GEN
SET V_DS(off) = 10 V
INPUT R_K
R_GG
50
W
V_GG
V_DD
R_D
R_T
50
W
INPUT PULSE
t_r ≤ 0.25 ns
t_f ≤ 0.5 ns
PULSE WIDTH = 2.0 ms
DUTY CYCLE ≤ 2.0%
R_GG > R_K
R_D’ = R_D(R_T + 50)
R_D + R_T + 50
Figure 5. Switching Time Test Circuit
OUTPUT
The switching characteristics shown above were measured using
a test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (−V_GG). The
Drain−Source Voltage (V_DS) is slightly lower than Drain Supply
Voltage (V_DD) due to the voltage divider. Thus Reverse Transfer
Capacitance (C_rss) of Gate−Drain Capacitance (C_gd) is charged to
V_GG + V_DS.
During the turn−on interval, Gate−Source Capacitance (C_gs)
discharges through the series combination of R_Gen and R_K. C_gd must
discharge to V_DS(on) through R_G and R_K in series with the parallel
combination of effective load impedance (R’_D) and Drain−Source
Resistance (r_DS). During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel
resistance r_DS is a function of the gate−source voltage. While C_gs
discharges, V_GS approaches zero and r_DS decreases. Since C_gd
discharges through r_DS, turn−on time is non−linear. During turn−off,
the situation is reversed with r_DS increasing as C_gd charges.
The above switching curves show two impedance conditions; 1)
R_K is equal to R_D’ which simulates the switching behavior of
cascaded stages where the driving source impedance is normally the
load impedance of the previous stage, and 2) R_K = 0 (low
impedance) the driving source impedance is that of the generator.
20
10
MMBF4393
7.0
5.0
3.0
MMBF4392
T_channel = 25°C
V_DS = 15 V
MMBF4391
2.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10 20 30 50
I_D, DRAIN CURRENT (mA)
Figure 6. Typical Forward Transfer Admittance
200 _{IDSS 25 mA}
= 10
160 ^mA
50 mA
75 mA 100 mA
125 mA
120
80
40
T_channel = 25°C
0 _{0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0}
V_GS, GATE−SOURCE VOLTAGE (VOLTS)
Figure 8. Effect of Gate−Source Voltage
on Drain−Source Resistance
15
10
C_gs
7.0
5.0
C_gd
3.0
T_channel = 25°C
2.0
(C_ds is negligible
1.5
1.0
0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10
30
V_R, REVERSE VOLTAGE (VOLTS)
Figure 7. Typical Capacitance
2.0
1.8
I_D = 1.0 mA
V_GS = 0
1.6
1.4
1.2
1.0
0.8
0.6
0.4−70 _{−40 −10 20 50 80 110 140 170}
T_channel, CHANNEL TEMPERATURE (°C)
Figure 9. Effect of Temperature on Drain−Source
On−State Resistance
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