MC74HC73A Datasheet, PDF (4/9 Pages) ON Semiconductor – Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS

MC74HC73A
SWITCHING WAVEFORMS
t_f
t_r
90%
V_CC
CLOCK
50%
10%
GND
t_w
1/f_max
t_PLH
t_PHL
90%
Q or Q 50%
10%
t_TLH
t_THL
Figure 1.
t_w
V_CC
RESET
50%
GND
t_PHL
Q
50%
t_PLH
Q
50%
t_rec
CLOCK
V_CC
50%
GND
Figure 2.
J or K
CLOCK
RESET ^{2, 6}
J ^{14, 7}
K ^{3, 10}
1, 5
CLOCK
VALID
t_su
t_h
50%
Figure 3.
V_CC
TEST POINT
GND
OUTPUT
V_CC
DEVICE
UNDER
TEST
C_L*
GND
*Includes all probe and jig capacitance
Figure 4.
EXPANDED LOGIC DIAGRAM
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
12, 9 _Q
CL
CL
13, 8 _Q
CL
CL
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