MC74HC73A Datasheet, PDF (1/9 Pages) ON Semiconductor – Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS

MC74HC73A
Dual J-K Flip-Flop with
Reset
High−Performance Silicon−Gate CMOS
The MC74HC73A is identical in pinout to the LS73. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has an active−low
asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a
different pinout.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 92 FETs or 23 Equivalent Gates
• These are Pb−Free Devices
LOGIC DIAGRAM
14
J1
1
CLOCK 1
3
K1
12
Q1
13
Q1
2
RESET 1
7
J2
5
CLOCK 2
10
K2
9
Q2
8
Q2
RESET 2
6
PIN 4 = V_CC
PIN 11 = GND
PIN ASSIGNMENT
CLOCK 1 1
RESET 1 2
K1 3
V_CC 4
CLOCK 2 5
RESET 2 6
J2 7
14 ^J1
13 Q1
12 Q1
11 GND
10 K2
9 Q2
8 Q2
14
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
1
MC74HC73AN
AWLYYWWG
14
1
14
SOIC−14
D SUFFIX
CASE 751A
1
HC73AG
AWLYWW
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
HC
73A
ALYWG
G
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
FUNCTION TABLE
Inputs
Outputs
Reset Clock J K Q Q
L
XXXLH
H
L L No Change
H
LHLH
H
HLHL
H
HH
Toggle
H
L X X No Change
H
H X X No Change
H
X X No Change
© Semiconductor Components Industries, LLC, 2009
1
December, 2009 − Rev. 7
Publication Order Number:
MC74HC73/D