MC74HC73A Datasheet, PDF (2/9 Pages) ON Semiconductor – Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS

MC74HC73A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V_CC DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V_in DC Input Voltage (Referenced to GND)
– 1.5 to V_CC + 1.5 V
V_out DC Output Voltage (Referenced to GND)
– 0.5 to V_CC + 0.5 V
I_in
DC Input Current, per Pin
± 20
mA
I_out DC Output Current, per Pin
± 25
mA
I_CC DC Supply Current, V_CC and GND Pins
± 50
mA
P_D Power Dissipation in Still Air
Plastic DIP†
750
mW
SOIC Package†
500
T_stg Storage Temperature
– 65 to + 150
_C
T_L Lead Temperature, 1 mm from Case for 10 Seconds
_C
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max Unit
V_CC DC Supply Voltage (Referenced to GND)
2.0 6.0 V
V_in, V_out DC Input Voltage, Output Voltage (Referenced to GND)
0
V_CC
V
T_A
Operating Temperature, All Package Types
– 55 + 125 _C
t_r, t_f
Input Rise and Fall Time
(Figure 1)
V_CC = 2.0 V 0
V_CC = 4.5 V 0
V_CC = 6.0 V 0
1000 ns
500
400
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
V_CC
Test Conditions
V
V_IH
Minimum High−Level Input
V_out = 0.1 V or V_CC – 0.1 V
2.0
Voltage
|I_out| v 20 μA
4.5
6.0
V_IL
Maximum Low−Level Input
V_out = 0.1 V or V_CC – 0.1 V
2.0
Voltage
|I_out| v 20 μA
4.5
6.0
V_OH
Minimum High−Level Output
V_in = V_IH or V_IL
2.0
Voltage
|I_out| v 20 μA
4.5
6.0
V_OL
Maximum Low−Level Output
Voltage
V_in = V_IH or V_IL |I_out| v 4.0 mA 4.5
|I_out| v 5.2 mA 6.0
V_in = V_IH or V_IL
2.0
|I_out| v 20 μA
4.5
6.0
V_in = V_IH or V_IL |I_out| v 4.0 mA 4.5
|I_out| v 5.2 mA 6.0
I_in
Maximum Input Leakage Current V_in = V_CC or GND
6.0
I_CC
Maximum Quiescent Supply
V_in = V_CC or GND
6.0
Current (per Package)
I_out = 0 μA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V_in and
V_out should be constrained to the
range GND v (V_in or V_out) v V_CC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V_CC).
Unused outputs must be left open.
Guaranteed Limit
– 55 to
25_C v 85_C v 125_C _Unit
1.5
1.5
1.5
V
3.15
3.15
3.15
4.2
4.2
4.2
0.3
0.3
0.3
V
0.9
0.9
0.9
1.2
1.2
1.2
1.9
1.9
1.9
V
4.4
4.4
4.4
5.9
5.9
5.9
3.98
3.84
3.70
5.48
5.34
5.20
0.1
0.1
0.1
V
0.1
0.1
0.1
0.1
0.1
0.1
0.26
0.33
0.40
0.26
0.33
0.40
± 0.1
± 1.0
± 1.0
μA
4
40
80
μA
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