74HC74 Datasheet, PDF (4/8 Pages) NXP Semiconductors – Dual D-type flip-flop with set and reset; positive-edge trigger

TIMING REQUIREMENTS (Input t_r = t_f = 6.0 ns)
74HC74
Symbol
Parameter
t_su Minimum Setup Time, Data to Clock
(Figure 3)
t_h
Minimum Hold Time, Clock to Data
(Figure 3)
t_rec Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
t_w
Minimum Pulse Width, Clock
(Figure 1)
t_w
Minimum Pulse Width, Set or Reset
(Figure 2)
t_r, t_f Maximum Input Rise and Fall Times
(Figures 1, 2, 3)
Guaranteed Limit
V_CC
– 55 to
(V)
25_C v 85_C v 125_C _Unit
2.0
80
3.0
35
4.5
16
6.0
14
100
120
ns
45
55
20
24
17
20
2.0
3.0
3.0
3.0
ns
3.0
3.0
3.0
3.0
4.5
3.0
3.0
3.0
6.0
3.0
3.0
3.0
2.0
8.0
8.0
8.0
ns
3.0
8.0
8.0
8.0
4.5
8.0
8.0
8.0
6.0
8.0
8.0
8.0
2.0
60
75
90
ns
3.0
25
30
40
4.5
12
15
18
6.0
10
13
15
2.0
60
75
90
ns
3.0
25
30
40
4.5
12
15
18
6.0
10
13
15
2.0
1000
1000
1000
ns
3.0
800
800
800
4.5
500
500
500
6.0
400
400
400
ORDERING INFORMATION
Device
Package
Shipping^†
74HC74D
74HC74DG
SOIC−14
SOIC−14
(Pb−Free)
55 Units / Rail
74HC74DR2
SOIC−14
74HC74DR2G
74HC74DTR2
SOIC−14
(Pb−Free)
TSSOP−14*
2500 / Tape & Reel
74HC74DTR2G
TSSOP−14*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
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