74HC74 Datasheet, PDF (3/8 Pages) NXP Semiconductors – Dual D-type flip-flop with set and reset; positive-edge trigger

74HC74
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
V_IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V_out = 0.1 V or V_CC – 0.1 V
|I_out| v 20 mA
V_CC
– 55 to
(V)
25_C v 85_C v 125_C _Unit
2.0
1.5
1.5
1.5
V
3.0
2.1
2.1
2.1
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V_IL Maximum Low−Level Input
Voltage
V_out = 0.1 V or V_CC – 0.1 V
|I_out| v 20 mA
2.0
0.5
0.5
0.5
V
3.0
0.9
0.9
0.9
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V_OH Minimum High−Level Output
Voltage
V_in = V_IH or V_IL
|I_out| v 20 mA
2.0
1.9
1.9
1.9
V
4.5
4.4
4.4
4.4
6.0
5.9
5.9
5.9
V_in = V_IH or V_IL |I_out| v 2.4 mA 3.0
2.48
2.34
2.2
|I_out| v 4.0 mA 4.5
3.98
3.84
3.7
|I_out| v 5.2 mA 6.0
5.48
5.34
5.2
V_OL Maximum Low−Level Output
Voltage
V_in = V_IH or V_IL
|I_out| v 20 mA
2.0
0.1
0.1
0.1
V
4.5
0.1
0.1
0.1
6.0
0.1
0.1
0.1
V_in = V_IH or V_IL |I_out| v 2.4 mA 3.0
0.26
0.33
0.4
|I_out| v 4.0 mA 4.5
0.26
0.33
0.4
|I_out| v 5.2 mA 6.0
0.26
0.33
0.4
I_in
Maximum Input Leakage Current V_in = V_CC or GND
6.0
±0.1
±1.0
±1.0
mA
I_CC Maximum Quiescent Supply
Current (per Package)
V_in = V_CC or GND
I_out = 0 mA
6.0
2.0
20
80
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
V_CC
– 55 to
(V)
25_C v 85_C v 125_C _Unit
f_max Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
6.0
4.8
4.0
MHz
3.0
15
10
8.0
4.5
30
24
20
6.0
35
28
24
t_PLH,
t_PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
100
125
150
ns
3.0
75
90
120
4.5
20
25
30
6.0
17
21
26
t_PLH,
t_PHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0
105
130
160
ns
3.0
80
95
130
4.5
21
26
32
6.0
18
22
27
t_TLH,
t_THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
C_in Maximum Input Capacitance
—
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Flip−Flop)*
32
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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