KAE02150 Datasheet, PDF (36/40 Pages) ON Semiconductor – Interline CCD Image Sensor

KAE−02150
Long Integrations and Readout
For extended integrations the output amplifiers need to be
powered down. When powered up, the output amplifiers
emit near infrared light that is sensed by the photodiodes. It
will begin to be visible in images of 30 second integrations
or longer.
To power down the output amplifiers set VDD1 and VSS1
to 0 V, and VDD23 to +5 V. Do not set VDD23 to 0 V during
the integration of an image. During the time the VDD2
supply is reduced to +5 V the substrate voltage reference
output SUBV will be invalid. For cameras with long
integration times, the value of SUBV will have to digitized
by and ADC and stored at the time when VDD23 is +15 V.
The SUB pin voltage would be set by a DAC. The HCCD
and EMCCD may be continue to clock during integration.
If they are stopped during integration then the EMCCD
should be re-started at +7 V to flush out any undesired signal
before increasing the voltage to charge multiplying levels.
The timing flow chart for long integration time is shown
in Figure 41.
Stop All VCCD Clocks at
the V_LOW (−8 V) Level.
Pulse the Electronic Shutter on VSUB
to Empty All Photodiodes.
Integration Begins on the Falling Edge
of the Electronic Shutter Pulse.
Set VDD23 = +5.0 V
Set VDD1 = 0.0 V
Set VSS1 = 0.0 V
Wait…
Set VDD23 = +15.0 V
Set VDD1 = +5.0 V
Set VSS1 = −8.0 V
Begin Normal Line Timing
Repeat for at Least 2,048 Lines
in Single or Dual Output Mode,
1,024 Lines in Quad Output
Mode.
Readout the Photodiodes
and One Image.
Figure 41. Timing Flow Chart for Long Integration Time
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