KAE02150 Datasheet, PDF (34/40 Pages) ON Semiconductor – Interline CCD Image Sensor

Electronic Shutter
VSUB
KAE−02150
V_AB + V_ES
HCCD
V_AB
3.3 V
0V
VCCD
t_VB
t_SUB
t_VB
0V
−8 V
Last HCCD
Clock Edge
First VCCD
Clock Edge
CAUTION: Do not clock the EMCCD register while the electronic shutter pulse is high.
Figure 38. Electronic Shutter Timing Pattern S1
Clock
H1S
H2S
H2SW
H2L
H2X
H1SEM
H1BEM
H2SEM
H2BEM
State
High
Low
Low
Low
Low
High
High
Low
Low
Figure 39. The State of the HCCD and EMCCD Clocks during the Frame, Line,
and Electronic Shutter Timing Sequences
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