LC87F0808AUQFPTLM-H Datasheet, PDF (3/25 Pages) ON Semiconductor – 8-bit 1-chip Microcontroller

LC87F0808A
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC/32 tCYC/128 tCYC)
Clock Output Function
• Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as
the system clock.
• Can generate the source clock for the subclock
Analog Comparator / Amplifier × 2 channels
• Analog comparator / amplifier selectable (each channel)
• Analog comparator Interrupt
MCPWM: Motor Control 12-bit PWM × 6 channels
• Dead time is programmable.
• Forced stop is possible by the output of the analog comparator and the INT terminals.
• Edge-aligned / center-aligned selectable
Watchdog Timer
• Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed
RC oscillation clock (30kHz).
• Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/HOLD mode.
Interrupts
• 21 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/Base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit/MCPWM
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/CMP1/CMP2
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 128levels (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits (12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits (12 tCYC execution time)
No.A1828-3/25