CAT5251_13 Datasheet, PDF (3/15 Pages) ON Semiconductor – Quad Digital Potentiometer (POT)

CAT5251
PIN DESCRIPTIONS
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5251. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT5251. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT5251. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5251.
R_H, R_L: Resistor End Points
The four sets of R_H and R_L pins are equivalent to the
terminal connections on a mechanical potentiometer.
R_W: Wiper
The four R_W pins are equivalent to the wiper terminal of
a mechanical potentiometer.
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT5251
and CS high disables the CAT5251. CS high takes the SO
output pin to high impedance and forces the devices into a
Standby mode (unless an internal write operation is
underway). The CAT5251 draws ZERO current in the
Standby mode. A high to low transition on CS is required
prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what initiates
an internal write cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high. When
WP is tied low, all non-volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT5251 while in the middle of a serial sequence without
having to re-transmit entire sequence at a later time. To
pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part
is paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to V_CC or
tied to V_CC through a resistor.
Table 1. PIN DESCRIPTION
Pin # Name
Function
1
SO Serial Data Output
2
A0
Device Address, LSB
3
R_W3 Wiper Terminal for Potentiometer 3
4
R_H3 High Reference Terminal for
Potentiometer 3
5
R_L3 Low Reference Terminal for
Potentiometer 3
6
NC No Connect
7
V_CC Supply Voltage
8
R_L0 Low Reference Terminal for
Potentiometer 0
9
R_H0 High Reference Terminal for
Potentiometer 0
10
R_W0 Wiper Terminal for Potentiometer 0
11
CS Chip Select
12
WP Write Protection
13
SI
Serial Input
14
A1
Device Address
15
R_L1 Low Reference Terminal for
Potentiometer 1
16
R_H1 High Reference Terminal for
Potentiometer 1
17
R_W1 Wiper Terminal for Potentiometer 1
18
GND Ground
19
NC No Connect
20
R_W2 Wiper Terminal for Potentiometer 2
21
R_H2 High Reference Terminal for
Potentiometer 2
22
R_L2 Low Reference Terminal for
Potentiometer 2
23
SCK Bus Serial Clock
24 HOLD Hold
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