CAT5251_13 Datasheet, PDF (10/15 Pages) ON Semiconductor – Quad Digital Potentiometer (POT)

CAT5251
HIGH, the selected wiper will move one resistor segment
towards the R_H terminal. Similarly, for each SCK clock
pulse while SI is LOW, the selected wiper will move one
resistor segment towards the R_L terminal.
See Instructions format for more detail.
SI
0101 00
ID3 ID2 ID1 ID0 _{A3 A2 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0}
Device ID
Internal
Address
Instruction _{Register Pot/WCR}
Opcode
Address Address
Figure 6. Two-byte Instruction Sequence
SI
0 10100
ID3 ID2 ID1 ID0 A3 A2 A1 A0 ^{I3 I2 I1 I0} R1 R0 P1 P0 ^{D7 D6 D5 D4 D3 D2 D1 D0}
Device ID
Internal
Address
Instruction _{Data Pot/WCR}
Opcode _{Register Address}
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 7. Three-byte Instruction Sequence
SI
010100
ID3 ID2 ID1 ID0 A3 A2 A1 A0 I3 I2 I1 I0 _{R1 R0 P1 P0 I I}
ID
D
Device ID
Internal
Address
Instruction
NN
Data ^{Pot/WCR C} C
NE
CC
E
C
Opcode
Register ^{Address 1 2}
n1
n
Address
Figure 8. Increment/Decrement Instruction Sequence
INC/DEC
Command
Issued
SCK
t_WRL
SI
Voltage Out
R_W
Figure 9. Increment/Decrement Timing Limits
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