CAT34TS02_13 Datasheet, PDF (3/20 Pages) ON Semiconductor – Digital Output Temperature Sensor with On-board SPD EEPROM

CAT34TS02
Table 5. A.C. CHARACTERISTICS (V_CC = 3.3 V ± 10%, T_A = −20°C to +125°C) (Note 4)
Symbol
Parameter
Min
Max
Units
F_SCL (Note 5)
Clock Frequency
10
400
kHz
t_HIGH
High Period of SCL Clock
600
ns
t_LOW
Low Period of SCL Clock
1300
ns
t_TIMEOUT (Note 5)
SMBus SCL Clock Low Timeout
25
35
ms
t_R (Note 6)
SDA and SCL Rise Time
300
ns
t_F (Note 6)
SDA and SCL Fall Time
300
ns
t_SU:DAT (Note 7)
Data Setup Time
100
ns
t_SU:STA
START Condition Setup Time
600
ns
t_HD:STA
START Condition Hold Time
600
ns
t_SU:STO
STOP Condition Setup Time
600
ns
t_BUF
Bus Free Time Between STOP and START
1300
ns
t_HD:DAT
Input Data Hold Time
0
ns
t_DH (Note 6)
Output Data Hold Time
200
900
ns
T_i
Noise Pulse Filtered at SCL and SDA Inputs
100
ns
t_WR
Write Cycle Time
5
ms
t_PU (Note 8)
Power−up Delay to Valid Temperature Recording
100
ms
4. Timing reference points are set at 30%, respectively 70% of V_CC, as illustrated in Figure 23. Bus loading must be such as to allow meeting
the V_IL, V_OL as well as the various timing limits.
5. For the CAT34TS02 Rev. B, the TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the t_TIMEOUT limit.
The time−out count is started (and then re−started) on every negative transition of SCL in the time interval between START and STOP. The
minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02’s SPD
component is DC, while the minimum operating frequency for the TS component is limited only by the SMBus time−out. For the CAT34TS02
Rev. C, both the TS and the SPD implement the time−out feature.
6. In a “Wired−OR” system (such as I²C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the V_IL and/or V_OL limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t_R limit, as long as it does not exceed t_LOW − t_DH − t_SU:DAT, where t_LOW
and t_DH are actual values (rather than spec limits). A shorter t_DH leaves more room for a longer SDA t_R, allowing for a more capacitive bus
or a larger bus pull−up resistor. At the minimum t_LOW spec limit of 1300 ns, the maximum t_DH of 900 ns demands a maximum SDA t_R of 300 ns.
The CAT34TS02’s maximum t_DH is <700 ns, thus allowing for an SDA t_R of up to 500 ns at minimum t_LOW.
7. The minimum t_SU:DAT of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a t_SU:DAT of 0 ns.
8. The first valid temperature recording can be expected after t_PU at nominal supply voltage.
Table 6. PIN CAPACITANCE (T_A = 25°C, V_CC = 3.3 V, f = 1 MHz)
Symbol
Parameter
Test Conditions/Comments
Min
Max
Unit
C_IN
SDA, EVENT Pin Capacitance
Input Capacitance (other pins)
V_IN = 0
V_IN = 0
8
pF
6
pF
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