AND8079 Datasheet, PDF (3/20 Pages) ON Semiconductor – A Low Cost DDR Memory Power Supply Using the NCP1571 Synchronous Buck Converter and a LM358 Based Linear Voltage Regulator

Q1
MTB1306
D2 PAK
TP5
5 V_Input
TP6
GND_Input
TP7
12 V_Input
TP8
V_Logic
TP9
V_5P0_STBV
TP10
-12 V_Input
L1
1mH
C1
1800mF
10V
R1
10
C12
0.1mF
R2
47k
C13
0.01mF
C24
1mF
C2
1800mF
10V
C3
1800mF
10V
C4
0.1mF
C5
1800mF
10V
Prov.
Q3
Q2
MTB1306
D2 PAK
L2
2.2mH
D1
MBRM110LT
PowerMite Prov.
R3
To = 1.0% 20k
NCP1571
U1
SO-8
1
VCC
2
PWRGD
3
PGDELAY
4
COMP
8
GND
7
Vfb
6
GATE(L)
5
GATE(H)
MTB1306
D2PAK
C6
100pF
Tol = 1.0% R4
13k
C7
1800mF
6.3V
Prov.
C8
C9
1800mF 0.1mF
6.3V
C10 ^C11
1800mF ^1800mF
6.3V ^6.3V
C14
0.1mF
C16
MC33375ST-2.5T3
SOT-223
U3 Prov.
1 _VIN
VOUT ³
2
4
ON OFF GND
4
2
3
U2A
LM358
Micro8
−
V- ^0.1mF
1
OUT
V+
8
C17
0.1mF
R7
1k
Q5
MTD20P03HDL
DPAK
TP1
2.5V
VDDQ (+2.5V, 8A)
Q4
NTD4302
D2 PAK
VTT (+1.25V, 2A)
TP2
1.25V_Vtt
C20
C21 C22 C23
1800mF 1800mF 0.1mF 1800mF
6.3V
Prov.
6.3V
Prov.
6.3V
TP3
GND_Output
C18
Tol. = 1.0% ^R5
10K
U2B
LM358
6_−
OUT ⁷
0.15mF
R8
200
5
Tol. = 1.0% ^R6
R9
C19
10K
C15
100
2mF
1mF
VREF (+1.25V, 2mA)
TP4
1.25V_Ref
Note: The provisional components were not used in the verification of the reference design.
Figure 2. DDR Memory Reference Design