AND8079 Datasheet, PDF(1/20 Page) ON Semiconductor – A Low Cost DDR Memory Power Supply Using the NCP1571 Synchronous Buck Converter and a LM358 Based Linear Voltage Regulator

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AND8079 Datasheet, PDF (1/20 Pages) ON Semiconductor – A Low Cost DDR Memory Power Supply Using the NCP1571 Synchronous Buck Converter and a LM358 Based Linear Voltage Regulator

AND8079/D

A Low Cost DDR Memory

Power Supply Using the

NCP1571 Synchronous Buck

Converter and a LM358

Based Linear Voltage

Regulator

Prepared by: Jim Lepkowski

Senior Application Engineer

http://onsemi.com

APPLICATION NOTE

INTRODUCTION

This application note describes a low cost power supply

circuit for a DDR (Double Data Rate) memory system. The

design is based on the NCP1570/NCP1571 low voltage

synchronous buck converter. The reference design created

to evaluate the system uses a 3.80â³ by 2.15â³ two layer printed

circuit board, optimized for a small solution size at an

economical cost.

DDR memories bring new challenges to the power supply

by requiring an efficient main power of 2.5 V (Vdd) and a

second voltage (Vtt) that accurately tracks one half of Vdd

(i.e. 1.25 V) that is capable of both sourcing and sinking

current. In addition, a third voltage is required (VREF) that

also tracks Vdd/2. A low voltage synchronous buck

converter is used to create an 8.0 A output at 2.5 V, while the

Vtt and VREF voltages are created using a unique operational

amplifier linear regulator circuit. The demonstration circuit

is designed for low power DDR systems such as desktop

PCs, but the circuitâs output power capability can be

increased with the selection of the external inductor and

capacitors for high power systems such as PC workstations.

DDR Memory Power Supply Requirements

Figure 1 shows a simplified schematic of the DDR

memory system. Voltage Vdd powers the memory ICs, in

addition to the buffer interface circuits. The termination

voltage Vtt is used for the pull-up resistors and must be able

to either sink or source current. For example, if all of the

driver circuits are at a logic high state (i.e. VOH = Vdd =

2.5 V), the Vtt supply will have to sink current in order to

maintain its 1.25 V. In contrast, if all of the driver circuits are

at a logic low state (i.e. VOL = Vss = 0 V), the Vtt supply will

have to source current because the termination resistors will

be effectively connected to ground.

Vdd

Transmitter

Vtt = Vdd/2

VREF

Receiver

Figure 1. DDR Memory Simplified Schematic

Vtt is equal to Vdd/2 instead of Vdd in order to save power.

The power dissipated in the resistors is equal to voltage

squared divided by the bus resistance, thus a termination

voltage of Vdd/2 provides a factor of four power savings.

The third voltage is used as a reference voltage to the

differential amplifier input section of the receiver ICs.

A summary of the specifications for the DDR memory

system is listed below. The transient requirements are not

defined in the industry JEDEC standards.

DDR

Voltage

Vdd

Vtt

VREF

Output

Voltage

2.5 V

Vdd/2

(^1.25 V)

Vdd/2

Tolerance

"200 mV

Vdd/2 " 3%

(1.250 V "

37.5 mV)

Vtt " 40 mV

Output Current

8.0 A

"2.0 A

(Sink and Source)

5.0 mA

October, 2002 - Rev. 1

Publication Order Number:

AND8079/D

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