AMIS-30532 Datasheet, PDF (24/29 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS--30532
Registers are updated with
the internal status at the
rising edge of CS
CS
The NEW DATA is written into the
correspondinginternal register at
the rising edge of CS
DI
DATA from previous
command or NOT VALID
after POR or RESET
DO
COMMAND
WRITE DATA
to ADDR2
DATA
OLD DATA
or NOT VALID
DATA
NEW DATA
for ADDR2
DATA
OLD DATA
from ADDR2
COMMAND
READ DATA
from ADDR2
DATA
OLD DATA
from ADDR2
COMMAND
or DUMMY
DATA
NEW DATA
from ADDR2
Figure 23. A WRITE Operation Where DATA from the Master is Written in SPI Register with Address 2 Followed
by a READ Back Operation to Confirm a Correct WRITE Operation
NOTE: The internal data--out shift buffer of AMIS--30532 is updated with the content of the selected SPI register only at the last (every
eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
Table 13. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to “0” after power--on or
hard reset)
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Reset
0
0
0
0
0
0
0
0
WR (00h)
Data
WDEN
WDT[3:0]
--
--
--
CR0 (01h)
Data
SM[2:0]
CUR[4:0]
CR1 (02h)
Data
DIRCTRL
NXTP
--
--
PWMF
PWMJ
EMC[1:0]
CR2 (03h)
Data
MOTEN
SLP
SLAG
SLAT
--
--
--
--
CR2 (08h)
Data
M[1:0]
StrB[1:0]
--
StrC
StrE[1:0]
Where:
R/W
Reset:
Read and Write access
Status after power--On or hard reset
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