AR023ZM Datasheet, PDF (22/35 Pages) ON Semiconductor – 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

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AR023ZM: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Electrical Specifications
Electrical Specifications
Unless otherwise stated, the following specifications apply under the following condi-
tions: VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V;
VDD_SLVS = 0.4V – 0.1/+0.2; T_A = -30°C to +85°C-40°C to +105°C; output load = 10pF;
frequency = 74.25 MHz; HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are
shown in Figure 9 and Table 5.
Figure 9: Two-Wire Serial Bus Timing Parameters
SDATA
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
tr
tBUF
SCLK
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
P
S
Note:
Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register
address are issued.
Table 5:
Two-Wire Serial Bus Characteristics
f_{EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; TA = 25°C}
Parameter
SCLK Clock Frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
LOW period of the SCLK clock
HIGH period of the SCLK clock
Set-up time for a repeated START
condition
Data hold time
Data set-up time
Rise time of both SDATA and SCLK signals
Fall time of both SDATA and SCLK signals
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Symbol
f_SCL
t_HD;STA
t_LOW
t_HIGH
t_SU;STA
t_HD;DAT
t_SU;DAT
t_r
t_f
t_SU;STO
t_BUF
Cb
Standard Mode
Min
Max
0
100
4.0
-
Fast Mode
Min
Max
Unit
0
400
KHz
0.6
-
s
4.7
-
1.3
-
s
4.0
-
0.6
-
s
4.7
-
0.6
-
s
0⁴
3.45⁵
0⁶
0.9⁵
s
250
-
100⁶
-
ns
-
1000
20 + 0.1Cb⁷
300
ns
-
300
20 + 0.1Cb⁷
300
ns
4.0
-
0.6
-
s
4.7
-
1.3
-
s
-
400
-
400
pF
AR0230CS_DS Rev. 4 Pub. 8/15 EN
22
©Semiconductor Components Industries, LLC, 2015.