AR023ZM Datasheet, PDF (20/35 Pages) ON Semiconductor – 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

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AR023ZM: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Features Overview
High Speed Serial Pixel (HiSPi) Interface
The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized
SP. The streaming protocols conform to a standard video application where each line of
active or intra-frame blanking provided by the sensor is transmitted at the same length.
The Packetized SP protocol will transmit only the active data ignoring line-to-line and
frame-to-frame blanking data.
The HiSPi interface building block is a unidirectional differential serial interface with
four data and one double data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple lanes. The AR023ZM
supports serial data widths of 10, 12, 14, 16, or 20 bits on one, two, or four lanes. The
specification includes a DLL to compensate for differences in group delay for each data
lane. The DLL is connected to the clock lane and each data lane, which acts as a control
master for the output delay buffers. Once the DLL has gained phase lock, each lane can
be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to
increase the setup or hold time at the receiver circuits and can be used to compensate
for skew introduced in PCB design. Delay compensation may be set for clock and/or
data lines in the hispi_timing register R0x31C0. If the DLL timing adjustment is not
required, the data and clock lane delay settings should be set to a default code of 0x0000
to reduce jitter, skew, and power dissipation.
Sensor Control Interface
The two-wire serial interface bus enables read/write access to control and status regis-
ters within the AR023ZM. The interface protocol uses a master/slave model in which a
master controls one or more slave devices. The sensor acts as a slave device. The master
generates a clock (SCLK) that is an input to the sensor and is used to synchronize trans-
fers.
Data is transferred between the master and the slave on a bidirectional signal (SDATA).
SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or master
device can drive SDATA LOW-the interface protocol determines which device is allowed
to drive SDATA at any given time. The two-wire serial interface can run at 100 kHz or 400
kHz.
T1/T2 Line Interleaved Mode
The AR023ZM has the capability to output the T1 and T2 exposures separately, in a line
interleaved format. The purpose of this is to enable off chip HDR linear combination
and processing. See the AR023ZM Developer Guide for more information.
AR0230CS_DS Rev. 4 Pub. 8/15 EN
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