AMIS-30511 Datasheet, PDF (22/28 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30511
SPI Control Registers
All SPI control registers have Read/Write access and default to “0” after power−on or hard reset.
Table 11. SPI Control Register 0
Control Register 0 (CR0)
Structure
Address
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Access
R/W
R/W
R/W
R/W
R/W
01h
Reset
0
0
0
0
0
Data
SM[2:0]
Where:
R/W
Reset:
SM[2:0]:
CUR[4:0]:
Read and Write access
Status after power−On or hard reset
Step mode
Current amplitude
Bit 2
R/W
0
CUR[4:0]
Table 12. SPI Control Register 1
Control Register 1 (CR1)
Structure
Address
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Access
R/W
R/W
R/W
R/W
R/W
02h
Reset
0
0
0
0
0
Data
DIRCTRL
NXTP
−
−
PWMF
Where:
R/W
Reset:
DIRCTRL
NXTP
PWMF
PWMJ
EMC[1:0]
Read and Write access
Status after power−on or hard reset
Direction control
NEXT polarity
PWM frequency
PWM jitter
EMC slope control
Bit 2
R/W
0
PWMJ
Table 13. SPI Control Register 2
Control Register 2 (CR2)
Structure
Address
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Access
R/W
R/W
R/W
R/W
R/W
R/W
03h
Reset
0
0
0
0
0
0
Data
MOTEN
SLP
SLAG
SLAT
−
−
Where:
R/W
Reset:
MOTEN
SLP
SLAG
SLAT
Read and Write access
Status after power−On or hard reset
Motor enable
Sleep
Speed load angle gain
Speed load angle transparency
Bit 1
R/W
0
Bit 0
R/W
0
Bit 1
Bit 0
R/W
R/W
0
0
EMC[1:0]
Bit 1
R/W
0
−
Bit 0
R/W
0
−
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