AMIS-30511 Datasheet, PDF (21/28 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30511
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
CS
COMMAND
DATA
DI
WRITE DATA to ADDR3
NEW DATA for ADDR3
DATA from previous command or
NOT VALID after POR or RESET
DATA
DATA
DO
OLD DATA or NOT VALID
OLD DATA from ADDR3
Figure 15. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3
Examples of Combined READ and WRITE Operations
In the following examples successive READ and WRITE
operations are combined. In Figure 13 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
by writing a control byte in Control Register at ADDR2.
Note that during the write command (in Figure 3) the old
data of the pointed register is returned at the moment the new
data is shifted in:
Registers are updated with the internal status at the rising
edge of the internal AMIS−30511 clock when CS = 1
CS
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
DI
DATA from previous command or
NOT VALID after POR or RESET
DO
COMMAND
READ DATA
from ADDR4
DATA
OLD DATA
or NOT VALID
COMMAND
READ DATA
from ADDR5
DATA
DATA
from ADDR4
COMMAND
WRITE
DATA to ADDR2
DATA
DATA
from ADDR5
DATA
NEW DATA
for ADDR2
DATA
OLD DATA
from ADDR2
Figure 16. 2 Successive READ Commands Followed by a WRITE Command
After the write operation the Master could initiate a read
back command in order to verify the data correctly written
as illustrated in Figure 14. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CSB line is high, the first read out byte
might represent old status information.
Registers are updated with the internal
status at the rising edge of CS
Registers are updated with the internal status at the rising
edge of the internal AMIS−30511 clock when CS = 1
CS
DI
Data from previous com-
mand or NOT VALID after
POR or RESET
DO
COMMAND
WRITE DATA
to ADDR2
DATA
OLD DATA
or NOT VALID
DATA
NEW DATA
for ADDR2
DATA
OLD DATA
from ADDR2
COMMAND
READ DATA
from ADDR2
DATA
OLD DATA
from ADDR2
COMMAND
or DUMMY
DATA
NEW DATA
from ADDR2
Figure 17. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2
Followed by a READ Back Operation to Confirm a Correct WRITE Operation
NOTE: The internal data−out shift buffer of AMIS−30511 is updated with the content of the selected SPI register only at the last (every
eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
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