AMIS-30521_10 Datasheet, PDF (20/28 Pages) ON Semiconductor – Micro-Stepping Motor Driver

#CLK Cycle
1
CS
AMIS−30521, NCV70521
2
3
4
5
6
7
8
CLK
DI
ÌÌÌÌÌÌÌÌ ^MSB
6
5
4
3
2
1
LSB
DO
MSB
6
5
4
3
2
1 LSB_{ÌÌÌÌÌÌ}
Figure 15. Timing Diagram of a SPI Transfer
NOTE: At the falling edge of the eighth clock pulse the data−out shift register is updated with the content of the addressed internal SPI
register. The internal SPI registers are updated at the first rising edge of the AMIS−30521/NCV70521 system clock when
CS = High.
Transfer Packet
Serial data transfer is assumed to follow MSB first rule.
The transfer packet contains one or more bytes.
BYTE 1
BYTE 2
Command and SPI Register Address
Data
MSB
LSB
MSB
LSB
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
D7
D6
D5
D4
D3
D2
D1
D0
Command
SPI Register Address
Figure 16. SPI Transfer Packet
PC20080630.6
Byte 1 contains the Command and the SPI Register
Address and indicates to the AMIS−30521/NCV70521 the
chosen type of operation and addressed register. Byte 2
contains data, or sent from the Master in a WRITE operation,
or received from the AMIS−30521/NCV70521 in a READ
operation.
Two command types can be distinguished in the
communication between Master and
AMIS−30521/NCV70521:
• READ from SPI Register with address ADDR[4:0]:
CMD[2:0] = “000”
• WRITE to SPI Register with address ADDR[4:0]:
CMD[2:0] = “100”
READ Operation
If the Master wants to read data from Status or Control
Registers, it initiates the communication by sending a
READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge
of the eighth clock pulse the data−out shift register is
updated with the content of the corresponding internal SPI
register. In the next 8−bit clock pulse train this data is shifted
out via DO pin. At the same time the data shifted in from DI
(Master) should be interpreted as the following successive
command or is dummy data.
Registers are updated with the internal status at the rising edge of the internal AMIS−30521/NCV70521 clock when CS = 1
CS
DI
DATA from previous command or NOT VALID
after POR or RESET
DO
COMMAND
READ Data from ADDR1
DATA
OLD DATA or NOT VALID
COMMAND or DUMMY
DATA
DATA from ADDR1
Figure 17. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master
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