CM1235 Datasheet, PDF (2/14 Pages) ON Semiconductor – Small Footprint PicoGuard XS® ESD Clamp Array For High Speed Data Line Protection

Block Diagram
CM1235
*Standard test condition is IEC61000-4-2 level 4 test circuit with each pin subjected to ±8kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous
test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes.
PicoGuard XS ESD Protection Architecture
Conceptually, an ESD protection device performs the following actions upon an ESD strike discharge into a
protected ASIC (see Figure 1):
1. When an ESD potential is applied to the system under test (contact or air-discharge), Kirchoff’s Current Law
(KCL) dictates that the Electrical Overstress (EOS) currents will immediately divide throughout the circuit,
based on the dynamic impedance of each path.
2. Ideally, the classic shunt ESD clamp will switch within 1ns to a low-impedance path and return the majority of
the EOS current to the chassis shield/reference ground. In actuality, if the ESD component's response time
(t_CLAMP) is slower than the ASIC it is protecting, or if the Dynamic Clamping Resistance (RDYN) is not signifi-
cantly lower than the ASIC's I/O cell circuitry, then the ASIC will have to absorb a large amount of the EOS
energy, and be more likely to fail.
3. Subsequent to the ESD/EOS event, both devices must immediately return to their original specifications, and
be ready for an additional strike. Any deterioration in parasitics or clamping capability should be considered a
failure, since it can then affect signal integrity or subsequent protection capability. (This is known as "multi-
strike" capability.)
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