CAT6243_16 Datasheet, PDF (2/15 Pages) ON Semiconductor – 1 Amp Adjustable CMOS LDO Voltage Regulator

CAT6243
VIN
VIN VOUT
ENABLE
C_IN
1 mF
CAT6243
BYP
ADJ
C_BYP
GND
(Optional)
VOUT
C_OUT
2.2 mF
Figure 1. Application Schematic
VIN
I_SENSE
Thermal
Shutdown
+
−
+
EN
Enable
Logic
V_REF ^−
2.5 M
VOUT
ADJ
BYP
GND
Figure 2. Simplified Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin #
WDFN−6
Pin #
DPAK−5−5
Pin Name
Description
1
5
EN
The Enable Input. An active HIGH input, turning ON the LDO. This input should be tied to
V_IN if the LDO is not intended to be shut off during normal operation. A pull−down 2.5 MW
resistor maintains the circuit in the OFF state if the pin is left open.
2, PAD
3, TAB
GND
Power Supply Ground; Device Substrate. The center pad is internally connected to Ground
and as such can cause short circuits to signal traces running beneath the IC. This pad is
intended for heat sinking the IC to the PCB and is typically connected to the PCB ground
plane.
3
NC
BYP
Bypass input. Placing a capacitor of 100 pF to 470 pF between BYP and ground reduces
noise on V_OUT. This capacitor is optional and it increases the turn−on time.
4
2
V_OUT
Regulated Output Voltage. A protection block eliminates any current flow from output to
input if V_OUT > V_IN.
5
1
ADJ
Output Voltage Adjust Input. This input ties to the common point of a resistor divider which
determines the regulator’s output voltage. See Applications section for details on selecting
resistor values.
6
4
V_IN
Positive Power Supply Input. Supplies power for V_OUT as well as the regulator’s internal
circuitry.
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