AMIS-30542 Datasheet, PDF (19/29 Pages) ON Semiconductor – AMIS-30542 Micro-Stepping Motor Driver

AMIS−30542
Error Output
This is a digital output to flag a problem to the external
microcontroller. The signal on this output is active low and
the logic combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR
<OVCYij> OR <OPENi> OR <CPFAIL>
Logic Supply Regulator
AMIS−30542 has an on−chip 5 V low−drop regulator
with external capacitor to supply the digital part of the chip,
some low−voltage analog blocks and external circuitry. The
voltage level is derived from an internal bandgap reference.
To calculate the available drive−current for external
VBB
circuitry, the specified I_load should be reduced with the
consumption of internal circuitry (unloaded outputs) and the
loads connected to logic outputs. See Table 5. DC
parameters
Power−On Reset (POR) Function
The open drain output pin POR/WD provides an “active
low” reset for external purposes. At powerup of
AMIS−30542, this pin will be kept low for some time to reset
for example an external microcontroller. A small analogue
filter avoids resetting due to spikes or noise on the V_DD
supply.
VDD
tPU
t
tPD
VDDH
V_DDL
t
< tRF
POR/WD pin
tPOR
t_RF
Figure 16. Power−on−Reset Timing Diagram
Watchdog Function
The watchdog function is enabled/disabled through
<WDEN> bit (Table 13: SPI CONTROL REGISTERS
(ALL SPI control registers have Read/Write Access and
default to “0” after power−on or hard reset.)). Once this bit
has been set to “1” (watchdog enable), the microcontroller
needs to re−write this bit to clear an internal timer before the
watchdog timeout interval expires. In case the timer is
activated and WDEN is acknowledged too early (before
t_WDPR) or not within the interval (after t_WDTO), then a reset
of the microcontroller will occur through POR/WD pin. In
addition, a warm/cold boot bit <WD> is available (see
Tables 16 and 17) for further processing when the external
microcontroller is alive again.
CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMIS−30542, the input
CLR needs to be pulled to logic 1 during minimum time
given by t_CLR. (Table 6 AC Parameters). This reset function
clears all internal registers without the need of a
power−cycle, except in sleep mode. The operation of all
analog circuits is depending on the reset state of the digital,
charge pump remains active. Logic 0 on CLR pin resumes
normal operation again.
The voltage regulator remains functional during and after
the reset and the POR/WD pin is not activated. Watchdog
function is reset completely.
Sleep Mode
The bit <SLP> in SPI Control Register 2 (See Table 12)
is provided to enter a so−called “sleep mode”. This mode
allows reduction of current−consumption when the motor is
not in operation. The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are forbidden
• SPI communication remains possible (slight current
increase during SPI communication)
• Oscillator and digital clocks are silent, except during
SPI communication
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