MT9D115 Datasheet, PDF (13/66 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9D115: 1/5-Inch SOC Digital Image Sensor
Architecture
Figure 6:
The external host interface is implemented through a two-wire interface that enables
direct read/write access to hardware registers and indirect access to firmware variables
within the MT9D115. The interface is designed to be compatible with the MIPI alliance
standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical characteris-
tics and transfer protocols of the two-wire serial interface specifications.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device to the external host which acts as a
master device. The master generates a clock (SCLK) that is an input to the sensor and
used to synchronize the transactions at the interface.
Data is transferred between the master and the slave on a bidirectional serial data bus
(SDATA). Both SCLK and SDATA are pulled up to VDD_IO off-chip by a 1.5K resistor.
Either the slave or master device can drive SDATA to LOW—the interface determines
which device is allowed to drive SDATA at any given time.
Two-Wire Serial Control Bus Timing
Write Sequence
t_SRTS
SCLK
t_SCLK
t_SRTH
t_SDS
t_SDH
t_SHAW
t_AHSW
t_STPS
t_STPH
SDATA
Write Start
Write
Address
Bit 7
Read Sequence
SCLK
Write
Address
Bit 0
Register
Ack
Value
Bit 7
t_SHAR
t_AHSR
t_SDHR
t_SDSR
Register
Value
Ack
Bit 0
Stop
SDATA
Read Start
Read
Address
Bit 7
Read
Address
Bit 0
Register
Value
Ack
Bit 7
Register
Value
Bit 0
MT9D115 DS Rev. E Pub. 4/15 EN
13
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