NCP1632 Datasheet, PDF (12/25 Pages) ON Semiconductor – Interleaved, 2-Phase Power Factor Controller

NCP1632
zero. The NCP1632 detects this falling edge and prevents
any new current cycle until it is detected.
Figure 8 shows how it is implemented.
For each phase, a ZCD comparator detects when the
voltage of the ZCD winding exceeds its upper threshold
(0.5 V typically). When this is the case, the coil is in
demagnetization phase and the latch L_ZCD is set. This latch
is reset when the next driver pulse occurs. Hence the output
of this latch (Q_ZCD) is high during the whole off−time
(demagnetization time + any possible dead time). The
output of the comparator is also inverted to form a signal
which is AND’d with the Q_ZCD output so that the AND gate
output (V_ZCD) turns high when the V_AUX voltage goes
below zero (below the 0.25 V lower threshold of the ZCD
comparator to be more specific). As a result, the ZCD
circuitry detects the V_AUX falling edge.
It is worth noting that as portrayed by Figure 9, V_AUX is
also representative of the MOSFET drain−source voltage
(“V_DS”). More specifically, when V_AUX is below zero, V_DS
is minimal (below the input voltage V_IN). That is why
V_ZCD is used to enable the driver so that the MOSFET turns
on when its drain−source voltage is low. Valley switching
reduces the losses and interference.
Rzcd2
1 ZCD2
Negative
and
positive
clamp
16 ZCD1
Rzcd1
D1
Vin
Negative
and
positive
clamp
+
−
0.5 V
OFF
V_DMG1
AND1
Vzcd1
PWM
SET1 ^latch
S
Qzcd1
PH1 Vcc
Q
L_{ZCD QZCD}
SQ
R
CLK1
R
(from phase
management ^In−rush
output
buffe r 1
block)
200− ms
reset signal
de lay
S
DT
Q
R
(from PH1 PWM
comparator)
(from Fault
L1
DRV1
14 M1
D2
Vin L2
Vout
management
block)
V_DMG2
+
−
0.5 V
Vzcd2
PWM
output
SET2 _{latch PH2 buffe r 2}
S ^Qzcd2
Q
CLK2
R
(from phase
S
Vcc
Q
R
management ^In−rush
reset signal
DRV2
Cbulk
11 M2
Cbulk
block) (from PH2 PWM comparator)
Figure 8. Zero Current Detection
At startup or after an inactive period (because of a
protection that has tripped for instance), there is no energy
in the ZCD winding and therefore no voltage signal to
activate the ZCD comparator. This means that the driver
will never turn on. To avoid this, an internal watchdog
timer is integrated into the controller. If the driver remains
low for more than 200 ms (typical), the timer sets the L_ZCD
latch as the ZCD winding signal would do. Obviously, this
200 ms delay acts as a minimum off−time if there is no
demagnetization winding voltage is detected.
To prevent negative voltages on the ZCD pins (ZCD1 for
phase 1 and ZCD2 for phase 2), these pins are internally
clamped to about 0 V when the voltage applied by the
corresponding ZCD winding is negative. Similarly, the
ZCD pins are clamped to V_ZCD(high) (10 V typical), when
the ZCD voltage rises too high. Because of these clamps,
a resistor (R_ZCD1 and R_ZCD2 of Figure 9) is necessary to
limit the current from the ZCD winding to the ZCD pin.
The clamps are designed to respectively source and sink
5 mA. It is hence recommended to dimension R_ZCD1 and
R_ZCD2 to limit the ZCD1 and ZCD2 pins current below
5 mA.
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