CAT28F010P-15 Datasheet, PDF (10/16 Pages) ON Semiconductor – 1 Megabit CMOS Flash Memory

CAT28F010
Figure 5. Chip Erase Algorithm⁽¹⁾
START ERASURE
APPLY VPPH
PROGRAM ALL
BYTES TO 00H
INITIALIZE
ADDRESS
INITIALIZE
PLSCNT = 0
WRITE ERASE
SETUP COMMAND
WRITE ERASE
COMMAND
BUS
OPERATION ^COMMAND
COMMENTS
STANDBY
VPP RAMPS TO VPPH
(OR VPP HARDWIRED)
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
INITIALIZE ADDRESS
PLSCNT = PULSE COUNT
WRITE
ERASE
ACTUAL ERASE
NEEDDAST1A0m=s2P0UHLSE,
DATA = 20H
WRITE
ERASE
DATA = 20H
TIME OUT 10ms
WAIT
WRITE ERASE
VERIFY COMMAND
WRITE
ERASE
VERIFY
ADDRESS = BYTE TO VERIFY
DATA = 24A000HHH;;
STOPS ERASE OPERATION
INCREMENT
ADDRESS
TIME OUT 6 s
READ DATA
FROM DEVICE
DATA =
NO
FFH?
YES
NO
LAST
ADDRESS?
YES
WRITE READ
COMMAND
APPLY VPPL
NO
INC PLSCNT
= 3100000 ?
YES
APPLY VPPL
READ
STANDBY
WAIT
READ BYTE TO
VERIFY ERASURE
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
WRITE
READ
STANDBY
DATA = 00H
RESETS THE REGISTER
FOR READ OPERATION
VPP RAMPS TO VPPL
(OR VPP HARDWIRED)
ERASURE
COMPLETED
ERASE
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. MD-1019, Rev. G
10
5108 FHD F10
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Characteristics subject to change without notice