CAT28F010P-15 Datasheet, PDF (1/16 Pages) ON Semiconductor – 1 Megabit CMOS Flash Memory

CAT28F010
1
Megabit
CMOS
Flash
Memory
Licensed Intel
second source
FEATURES
s Fast read access time: 90/120 ns
s Low power CMOS dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
s High speed programming:
–10 µs per byte
–2 Sec Typ Chip Program
s 0.5 seconds typical chip-erase
s 12.0V ± 5% programming and erase voltage
s Stop timer for program/erase
s Commercial, industrial and automotive
temperature ranges
s On-chip address and data latches
s JEDEC standard pinouts:
–32-pin DIP
–32-pin PLCC
–32-pin TSOP (8 x 20)
s 100,000 program/erase cycles
s 10 year data retention
s Electronic signature
DESCRIPTION
The CAT28F010 is a high speed 128K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and EEPROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F010 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
BLOCK DIAGRAM
I/O0–I/O7
ERASE VOLTAGE
SWITCH
I/O BUFFERS
WE
CE
OE
A0–A16
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
VOLTAGE VERIFY
SWITCH
Y-DECODER
X-DECODER
Y-GATING
1,048,576 BIT
MEMORY
ARRAY
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1019, Rev. G