CAT28C256N-20 Datasheet, PDF (10/14 Pages) ON Semiconductor – 256 kb Parallel EEPROM

CAT28C256
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 10). This sequence of commands
(along with subsequent writes) must adhere to the page write
timing specifications (Figure 12). Once this is done, all
subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection on
power−up in addition to the hardware protection provided.
DATA
ADDRESS
CE
AA
5555
55
2AAA
WE
To allow the user the ability to program the device with an
EEPROM programmer (or for testing purposes) there is a
software command sequence for deactivating the data
protection. The six step algorithm (Figure 11) will reset the
internal protection circuitry, and the device will return to
standard operating mode (Figure 13 provides reset timing).
After the sixth byte of this reset sequence has been issued,
standard byte or page writing can commence.
A0
5555
t_WP
t_WC
BYTE OR
PAGE
WRITES
t_BLC
ENABLED
Figure 12. Software Data Protection Timing
DATA
ADDRESS
CE
WE
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
t_WC
5555
SDP
RESET
DEVICE
UNPROTECTED
Figure 13. Resetting Software Data Protection Timing
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