MTD10N10EL_06 Datasheet, PDF (1/7 Pages) ON Semiconductor – TMOS E−FET Power Field Effect Transistor DPAK for Surface Mount

MTD10N10EL
TMOS E−FET™
Power Field Effect Transistor
DPAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
This advanced TMOS E−FET is designed to withstand high energy
in the avalanche and commutation modes. The new energy efficient
design also offers a drain−to−source diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
Features
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I_DSS and V_DS(on) Specified at Elevated Temperature
• Pb−Free Package is Available
MAXIMUM RATINGS (T_C = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (R_GS = 1.0 MW)
Gate−to−Source Voltage − Continuous
Non−Repetitive (t_p ≤ 10 ms)
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (t_p ≤ 10 ms)
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
Total Power Dissipation @ T_A = 25°C (Note 2)
Operating and Storage Temperature Range
V_DSS
V_DGR
V_GS
V_GSM
I_D
I_D
I_DM
P_D
T_J, T_stg
100 Vdc
100 Vdc
±15 Vdc
±20 Vpk
10 Adc
6.0
35 Apk
40
W
0.32 W/°C
1.75 W
−55 to °C
150
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 25 Vdc, V_GS = 5.0 Vdc, I_L = 10 Apk,
L = 1.0 mH, R_G = 25 W)
E_AS
mJ
50
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
R_θJC
R_θJA
R_θJA
°C/W
3.13
100
71.4
Maximum Temperature for Soldering
Purposes, 1/8″ from case for 10 sec
T_L
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using minimum recommended pad
size.
2. When surface mounted to an FR4 board using 0.5 sq in pad size.
http://onsemi.com
V_DSS
100 V
R_DS(ON) TYP
0.22 W
I_D MAX
10 A
N−Channel
D
G
S
MARKING DIAGRAM & PIN ASSIGNMENTS
4
Gate 1
YWW
12
3
DPAK
CASE 369C
Drain 2
10N
10ELG
Source 3
(Surface Mount)
STYLE 2
4
Drain
10N10EL
Y
WW
G
= Device Code
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping^†
MTD10N10ELT4 DPAK 2500 Tape & Reel
MTD10N10ELT4G DPAK 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 3
Publication Order Number:
MTD10N10EL/D