MC74LVX50_14 Datasheet, PDF (1/9 Pages) ON Semiconductor – Hex Buffer

MC74LVX50
Hex Buffer
The MC74LVX50 is an advanced high speed CMOS buffer
fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: t_PD = 4.1 ns (Typ) at V_CC = 3.3 V
• Low Power Dissipation: I_CC = 2 mA (Max) at T_A = 25°C
• High Noise Immunity: V_NIH = V_NIL = 28% V_CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 3.6 V Operating Range
• Low Noise: V_OLP = 0.5 V (Max)
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
V_CC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8
1
A1
3
A2
5
A3
9
A4
11
A5
13
A6
2
Y1
4
Y2
A1
1
Y1
6
Y3
A2
1
Y2
Y=A
8
A3
1
Y3
Y4
A4
1
Y4
10
Y5
A5
1
Y5
12
Y6
A6
1
Y6
Figure 1. Logic Diagram
Figure 2. Logic Symbol
FUNCTION TABLE
A Input
L
H
Y Output
L
H
1234567
A1 Y1 A2 Y2 A3 Y3 GND
14−Lead (Top View)
MARKING DIAGRAMS
14
LVX50G
AWLYWW
1
SOIC−14 NB
14
LVX
50
ALYWG
G
1
TSSOP−14
LVX50 = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 5
Publication Order Number:
MC74LVX50/D