A42MX09-PLG84M Datasheet, PDF (65/143 Pages) Omron Electronics LLC – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed
Min. Max. Min. Max. Min. Max. Min. Max.
–F Speed
Min. Max.
Units
Input Module Propagation Delays
t_INYH
Pad-to-Y HIGH
1.1
1.2
1.3
1.6
2.2 ns
t_INYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7 ns
t_INGH G to Y HIGH
1.4
1.6
1.8
2.1
2.9 ns
t_INGL
G to Y LOW
1.4
1.6
1.8
2.1
2.9 ns
Input Module Predicted Routing Delays²
t_IRD1
FO = 1 Routing Delay
t_IRD2
FO = 2 Routing Delay
t_IRD3
FO = 3 Routing Delay
t_IRD4
FO = 4 Routing Delay
t_IRD8
FO = 8 Routing Delay
Global Clock Network
1.8
2.0
2.3
2.7
4.0 ns
2.1
2.3
2.6
3.1
4.3 ns
2.3
2.6
3.0
3.5
4.9 ns
2.6
3.0
3.3
3.9
5.4 ns
3.6
4.0
4.6
5.4
7.5 ns
t_CKH
Input LOW to HIGH FO = 32
2.6
2.9
3.3
3.9
5.4 ns
FO = 384
2.9
3.2
3.6
4.3
6.0 ns
t_CKL
Input HIGH to LOW FO = 32
3.8
4.2
4.8
5.6
7.8 ns
FO = 384
4.5
5.0
5.6
6.6
9.2 ns
t_PWH
Minimum Pulse Width FO = 32
3.2
3.5
4.0
4.7
6.6
ns
HIGH
FO = 384 3.7
4.1
4.6
5.4
7.6
ns
t_PWL
Minimum Pulse Width FO = 32
3.2
3.5
4.0
4.7
6.6
ns
LOW
FO = 384 3.7
4.1
4.6
5.4
7.6
ns
t_CKSW Maximum Skew
FO = 32
0.3
0.4
0.4
0.5
0.7 ns
FO = 384
0.3
0.4
0.4
0.5
0.7 ns
t_SUEXT Input Latch External FO = 32
0.0
0.0
0.0
0.0
0.0
ns
Set-Up
FO = 384 0.0
0.0
0.0
0.0
0.0
ns
t_HEXT Input Latch External FO = 32
2.8
3.1
5.5
4.1
5.7
ns
Hold
FO = 384 3.2
3.5
4.0
4.7
6.6
ns
t_P
Minimum Period
FO = 32 4.2
4.67
5.1
5.8
9.7
ns
FO = 384 4.6
5.1
5.6
6.4
10.7
ns
f_MAX
Maximum Frequency FO = 32
237
215
198
172
103 MHz
FO = 384
215
195
179
156
94 MHz
Notes:
1.
For dual-module
appropriate.
macros,
use
t_PD1
+
t_RD1
+
t_PDn,
t_CO
+
t_RD1
+
t_PDn,
or
t_PD1
+
t_RD1
+
t_SUD,
point
and
position
whichever
is
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-61
Revision 12