W712 Datasheet, PDF (8/17 Pages) OKI electronic componets – Universal Serial Bus Controller 0.5uM Technology Mega Macrofunction

s W712 USB Device Controller s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
FIFO Interface
Signal
[7:0]trx_out_data
[7:0]rcv_out_data
[7:0]trx_in_data
[2:0]trx_sel
[8:0]trx_wr_ptr
[8:0]trx_rd_ptr
[6:0]trx_wrb
[7:0]rcv_in_data
[2:0]rcv_sel
[8:0]rcv_wr_ptr
[8:0]rcv_rd_ptr
[6:0]rcv_wrb
Type
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Assertion
—
—
—
HIGH
—
—
LOW
—
HIGH
—
—
LOW
Description
Transmit FIFO(s} data output. Output data from the transmission RAM selected for read-
ing.
Receive FIFO(s) data output. Output data from the receiving RAM selected for reading.
Transmit FIFO(s) data input. Input data to all transmission RAMs.
Transmit FIFO(s) select. Selects one of the seven transmission RAMs for reading.
Transmit FIFO(s) write pointer. Write address to all transmission RAMs.
Transmit FIFO(s) read pointer. Read address to all transmission RAMs.
Transmit FIFO(s) write strobe. Write enable. One bit per transmission RAM.
Receive FIFO(s) data input. Input data to all receiving RAMs.
Receive FIFO(s) select. Selects one of the seven receiving RAMs for reading.
Receive FIFO(s) write pointer. Write address to all receiving RAMs.
Receive FIFO(s) read pointer. Read address to all receiving RAMs.
Receive FIFO(s) write strobe. Write enable. One bit per receiving RAM.
DPLL Interface
Signal
osc_clk
usb_clk_ext
usb_rxd_out
Type
Input
Input
Output
Assertion
–
–
–
Description
Oscillator Clock. Attach a 48 MHz clock signal for full-speed operation or a 6 MHz clock
signal for low-speed operation.
USB Clock External. This is the output clock signal from an external DPLL. This clock
should run at 12 MHz for full-speed operation or 1.5 MHz for low-speed operation. If an
external DPLL is not used, this pin should be connected to VDD or GND.
Synchronized USB Differential Received Data. This signal comes from the USB differen-
tial receiver and is synchronized with the oscillator input. This signal connects to the ex-
ternal DPLL if it is used.
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Oki Semiconductor