W712 Datasheet, PDF (7/17 Pages) OKI electronic componets – Universal Serial Bus Controller 0.5uM Technology Mega Macrofunction

–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s W712 USB Device Controller s
Application Interface
Signal
sys_clock
Type
Input
sys_reset
Input
mwr_rdb
Input
usb_reset
[7:0]ma
[7:0]md
mrdyb
[7:0]pd
[3:0]pkt_rdy
full_spden
setup_rdy
iso_err
validsof
sel_ext_pll
setup_rdy2
testmode
validin
validout
Output
Input
Input
Input
Output
Output
Input
Output
Output
Output
Input
Output
Input
Output
Output
Assertion
—
HIGH
—
HIGH
—
—
LOW
—
HIGH
—
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
Description
Clock. Attach a 12-MHz clock signal to this input for full-speed operation and 1.5 MHz for
low-speed operation.
W712 Reset. Asserting this signal HIGH resets the W712 mega macrofunction. The appli-
cation module is required to assert this signal at power-on.
Write/Read Select. When external application logic asserts this signal HIGH, the applica-
tion is in WRITE mode. When asserted LOW, the application is in READ mode. External
application logic asserts this signal HIGH when writing data to the transmit FIFOs or to the
register files. External application logic asserts this signal LOW when reading data from
the receiving FIFOs or from the register files. The register files contain information describ-
ing the function and transaction status.
USB Reset. This is the reset signal from the USB device controller.
Address Bus. These eight inputs receive the address of the register files in the USB device
controller.
Input Data Bus. These eight inputs receive the data to be stored in the register files or
transmit FIFOs.
Data Strobe. When asserted LOW and in WRITE mode, the data on the [7:0]md signal
lines are valid for writing. When asserted LOW and in READ mode, the data on the [7:0]pd
signals are valid for reading.
Output Data Bus. These eight outputs transmit data received from either the register files
or the receive FIFOs.
Packet Ready. When the W712 asserts this signal, it indicates that one of the four receive
FIFOs contains valid data. The application reads the data through the [7:0]pd bus.
USB Full Speed Enable. The application module sets this pin to “1” to select full-speed
operation and “0” to select low-speed operation.
Setup Ready. Asserting this signal HIGH indicates an 8-byte SETUP data has been re-
ceived from the USB bus.
Isochronous Error. Used for loopback testing or to indicate isochronous data has been re-
ceived with DATA1 PID.
Valid SOF. This signal is asserted for two bit times, asynchronous to sys_clock, and indi-
cates a valid SOF token is received when asserted HIGH.
Select External PLL. Asserting this signal HIGH selects the external PLL option.
Second Setup Ready. Asserting this signal HIGH indicates a new 8-byte SETUP DATA has
been received, while internally the device controller still sees the “setup_rdy” signal assert-
ed. This signal will be asserted for two bit times, asynchronous to sys_clock.
Testmode. Asserting this signal invokes a loopback test mode.
Valid IN. Asserted for two bit times, asynchronous to sys_clock, and indicates a valid IN
token is received when asserted HIGH.
Valid OUT. Asserted for two bit times, asynchronous to sys_clock, and indicates a valid
OUT token is received when asserted HIGH.
Oki Semiconductor
5