MSC5301B-01 Datasheet, PDF (13/15 Pages) OKI electronic componets – LCD COMMON/SEGMENT DRIVER WITH RAM

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MSC5301B-01
Serial Signal to be Input From CPU
The following signals are input from an external CPU to this LCD driver.
- Serial transfer clock Æ SCK
- Serial transfer data Æ SI
- Serial transfer latch Æ LATCH
- Serial data select Æ A/D
The operations are shown in the following table.
Mode
A/D
SCK
LATCH
SI
Address data
input mode
Shifts at
8-bit address latch at falling 8-bit address data
H
the rising edge edge (level sensitive)
Serial input from LSB side
64-bit segment data
Segment data
Shifts at
64-bit segment data latch at
L
Serial input from S63 corresponding data
input mode
the rising edge falling edge (level sensitive) _{"1" : Display-on data, "0" : Display-off data}
Timing Chart of Serial Signal Transferred From CPU
A/D
"H" at address data setting
"L" at segment data setting
12 3 45 67 8
SCK
12 3
63 64
A0 A1 A2 A3 CS0 CS1 Dummy Dummy S63 S62 S61
SI
LSB
MSB
S1 S0
Address data (8 bits)
Segment data (64 bits)
LATCH
Address latch
signal
RAM write
signal
Notes:
1. Make sure to set the address before writing the segment data to RAM. Then, write the segment
data to RAM.
2. While the POR pin is "H" (upon power-on reset), neither the address data nor the segment
data can be entered.
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