MSC5301B-01 Datasheet, PDF (12/15 Pages) OKI electronic componets – LCD COMMON/SEGMENT DRIVER WITH RAM

¡ Semiconductor
MSC5301B-01
Multiple Configuration
This LCD driver can form multiple configuration.
It is possible to form a maximum of 4 devices (a panel of up to 256 ¥ 16 dots in size can be formed)
by using chip select signals CS0 and CS1. The devices in multiple configuration must be
synchronized with one another. In this configuration, one device in the master mode and the
other devices in the slave mode are used in combination. In the master mode, the original
oscillation signal f and the synchronous signal FRAM are output; in the slave mode, the
original oscillation signal f and the synchronous signal FRAM are input.
Refer to items CS0 and CS1 of pin description on the mode setting method.
The original oscillation signal output pin f of the master mode device is connected to the OS1
pin of the slave mode device and the synchronizing signal pin FRAM is also connected to the
FRAM pin of the slave mode device.
Connect SI, SCK, LATCH, A/D, POR and BLK of the master mode device to SI, SCK, LATCH,
A/D, POR and BLK of each of the slave mode devices and connect them to CPU for control.
In addition, connect the devices so that V_DSP, V₁, V₂, V₃, V₄ and GND are shared between the
devices, and connect them to each voltage level divided by external resistors.
Address Data Configuration
(MSB)
(LSB)
7654 3210
Dummy data Upper address
Lower address
DM DM CS1 CS0 A3 A2 A1 A0
2 bits
2 bits
4 bits
The lower address, which is the display RAM address, corresponds to the common sides C0
- C15 of the LCD panel.
The upper address corresponds to the logical state of chip select pins CS0 and CS1 and the lower
address is set to the device.
For the device to output the common signal (f, FRAM), set both of the upper address 2 bits to
"L". The 2 bits of dummy data can be set to either "L" or "H".
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