PCA9554B Datasheet, PDF (9/36 Pages) NXP Semiconductors – Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up

NXP Semiconductors
PCA9554B; PCA9554C
Low-voltage 8-bit I²C-bus/SMBus low power I/O port
7. Bus transactions
The PCA9554B/PCA9554C is an I²C-bus slave device. Data is exchanged between the
master and PCA9554B/PCA9554C through write and read commands using I²C-bus. The
two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor when connected to the
output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Write commands
Data is transmitted to the PCA9554B/PCA9554C by sending the device address and
setting the Least Significant Bit (LSB) to a logic 0 (see Figure 4 for device address). The
command byte is sent after the address and determines which register receives the data
that follows the command byte. There is no limitation on the number of data bytes sent in
one write transmission.
SCL 1 2 3 4 5 6 7 8 9
slave address⁽¹⁾
command byte
SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A
data to port
DATA 1
STOP
condition
AP
START condition
write to port
data out from port
R/W acknowledge
from slave
acknowledge
from slave
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 7. Write to Output port register
acknowledge
from slave
t_v(Q)
DATA 1 VALID
002aah124
SCL 1 2 3 4 5 6 7 8 9
slave address⁽¹⁾
command byte
SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 1/0 1/0 A
data to register
DATA 1
START condition
R/W acknowledge
from slave
acknowledge
from slave
(1) PCA9554B address shown. Address for PCA9554C is 0111,A2,A1,A0.
Fig 8. Write to Configuration or Polarity inversion registers
STOP
condition
AP
acknowledge
from slave
002aah125
PCA9554B_PCA9554C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 September 2012
© NXP B.V. 2012. All rights reserved.
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