PCA9554B Datasheet, PDF(8/36 Page) NXP Semiconductors – Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up

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PCA9554B Datasheet, PDF (8/36 Pages) NXP Semiconductors – Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up

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NXP Semiconductors

PCA9554B; PCA9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

6.6 Power-on reset

When power (from 0 V) is applied to VDD, an internal power-on reset holds the

PCA9554B/PCA9554C in a reset condition until VDD has reached VPOR. At that time, the

reset condition is released and the PCA9554B/PCA9554C registers and I2C-bus/SMBus

state machine initialize to their default states. After that, VDD must be lowered to below

VPORF and back up to the operating voltage for a power-reset cycle. See Section 8.2

âPower-on reset requirementsâ.

6.7 Interrupt output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.

After time tv(INT), the signal INT is valid. Resetting the interrupt circuit is achieved when

data on the port is changed to the original setting or when data is read from the port that

generated the interrupt (see Figure 10). Resetting occurs in the Read mode at the

acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL

signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very

short) due to the reset of the interrupt during this pulse. Each change of the I/Os after

resetting is detected and is transmitted as INT.

A pin configured as an output cannot cause an interrupt. Changing an I/O from an output

to an input may cause a false interrupt to occur, if the state of the pin does not match the

contents of the Input port register.

The INT output has an open-drain structure and requires a pull-up resistor to VDD. INT

should be connected to the voltage source of the device that requires the interrupt

information. When using the input latch feature, the input pin state is latched. The interrupt

is reset only when data is read from the port that generated the interrupt. The reset occurs

in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the

rising edge of the SCL signal.

PCA9554B_PCA9554C

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 â 19 September 2012

8 of 36

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