BUK100-50GS Datasheet, PDF (9/11 Pages) NXP Semiconductors – PowerMOS transistor TOPFET

Philips Semiconductors
PowerMOS transistor
TOPFET
Product specification
BUK100-50GS
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80 100 120 140
Tmb / C
Fig.26. Normalised limiting clamping energy.
E_DSM% = f(T_mb); conditions: I_D = 15 A; V_IS = 10 V
VDS
0
ID
0
VIS
0
V(CL)DSS
VDD
L
+ ^VDD
VDS
D
TOPFET
I
P
D.U.T.
-
-ID/100
RIS
Schottky
S
R 01
shunt
Fig.27. Clamping energy test circuit, R_IS = 50 Ω.
E_DSM = 0.5 ⋅ L I_D² ⋅ V_(CL)DSS/(V_(CL)DSS − V_DD)
Idss
1 mA
100 uA
10 uA
typ.
1 uA
100 nA
0
20
40
60
80 100 120 140
Tj / C
Fig.28. Typical off-state leakage current.
I_DSS = f(T_j); Conditions: V_DS = 40 V; I_IS = 0 V.
Iiso normalised to 25 C
1.5
1
0.5
-60
-20
20
60
100
140
180
Tj / C
Fig.29. Normalised input current (normal operation).
I_IS/I_IS25 ˚C = f(T_j); V_IS = 10 V
Iisl normalised to 25 C
1.5
1
0.5
-60
-20
20
60
100
140
180
Tj / C
Fig.30. Normalised input current (protection latched).
I_ISL/I_ISL25 ˚C = f(T_j); V_IS = 10 V
VDDP(P) / V
50
BUK100-50GS
40
max
30
20
10
0
0
2
4
6
8
10
VIS / V
Fig.31. Maximum drain source supply voltage for
SC load protection. V_DDP(P) = f(V_IS); T_mb ≤ 150 ˚C
November 1996
9
Rev 1.300