SSTUG32868 Datasheet, PDF (8/29 Pages) NXP Semiconductors – 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications

NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
6.2 Pin description
Table 3. Pin description
Symbol Pin
1 : 2 Register A (C = 0)
Ungated inputs
DCKE0 D1
DCKE1 C1
DODT0 N1
DODT1 P1
Chip Select gated inputs
D1 to
D28
A2, A1, B2, B1, C2, C1,
D2, D1, E1, F1, G1, H1,
N1, P1, R1, T1, U1, V1,
W1, W2, Y1, Y2, AA1,
AA2, AB1, AB2
Chip Select inputs
DCS0 K1
DCS1 J1
DCS2 K3
DCS3 P3
1 : 2 Register B (C = 1)
Type
W1
SSTL_18
Y1
K1
SSTL_18
J1
A2, A1, B2, B1, C2, C1, SSTL_18
D2, D1, E1, F1, G1, H1, J1,
K1, N1, P1, R1, T1, U1,
V1, W1, W2, Y1, Y2, AA1,
AA2, AB1, AB2
N1
SSTL_18
P1
K3
P3
Configuration control inputs
C
A3
A3
LVCMOS
input
Re-driven outputs
Q1A to
Q28A
A7, B7, C7, D7, E7, E2, F7,
F2, G7, G2, H7, H2, N2,
P2, R2, R7, T2, T7, U2,
U7, V2, V7, W7, Y7, AA7,
AB7
A7, B7, C7, D7, E7, E2, F7,
F2, G7, G2, H7, H2, J2,
K2, N2, P2, R2, R7, T2, T7,
U2, U7, V2, V7, W7, Y7,
AA7, AB7
1.8 V
CMOS
outputs
Q1B to
Q28B
A8, B8, C8, D8, E8, F8,
G8, H8, J8, J7, K8, K7, L8,
L7, M7, M8, N7, N8, P7,
P8, R8, T8, V8, U8, W8,
Y8, AA8, AB8
A8, B8, C8, D8, E8, F8,
G8, H8, J8, J7, K8, K7, L8,
L7, M7, M8, N7, N8, P7,
P8, R8, T8, U8, V8, W8,
Y8, AA8, AB8
QCS0A K2
QCS0B L7
QCS1A J2
N2
1.8 V
M7
CMOS
outputs
P2
QCS1B L8
M8
Description
The outputs of this register will not be
suspended by the DCS0 and DCS1
control.
The outputs of this register will not be
suspended by the DCS0 and DCS1
control.
Data inputs, clocked in on the crossing of
the rising edge of CK and the falling
edge of CK.
Chip select inputs. These pins initiate
DRAM address/command decodes, and
as such at least one will be LOW when a
valid address/command is present. The
register can be programmed to re-drive
all D-inputs (CSGEN = HIGH) only when
at least one chip select input is LOW. If
CSGEN, DCS0 and DCS1 inputs are
HIGH, D1 to D28^[1] inputs will be
disabled.
Configuration control inputs; Register A
or Register B
Data outputs^[2] that are suspended by
the DCS0 and DCS1 control.
Data outputs that will not be suspended
by the DCS0 and DCS1 control.
SSTUG32868_1
Product data sheet
Rev. 01 — 23 April 2007
© NXP B.V. 2007. All rights reserved.
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