SSTUG32868 Datasheet, PDF (19/29 Pages) NXP Semiconductors – 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications

NXP Semiconductors
SSTUG32868
1.8 V DDR2-1G configurable registered buffer with parity
11. Test information
11.1 Parameter measurement information for data output load circuit
V_DD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
Pulse Repetition Rate (PRR) ≤ 10 MHz; Z₀ = 50 Ω; input slew rate = 1 V/ns ± 20 %,
unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
50 Ω
CK inputs
test point
RL = 100 Ω
DUT
CK
OUT
CK
test point
(1) C_L includes probe and jig capacitance.
Fig 9. Load circuit, data output measurements
V_DD
delay = 350 ps
Zo = 50 Ω
CL = 30 pF(1)
RL = 1000 Ω
RL = 1000 Ω
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LVCMOS
RESET
0.5V_DD
I_DD(1)
t_INACT
10 %
0.5V_DD
V_DD
0V
t_ACT
90 %
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(1) I_DD tested with clock and data inputs held at V_DD or GND, and I_O = 0 mA.
Fig 10. Voltage and current waveforms; inputs active and inactive times
input
t_W
V_ICR
V_ICR
V_IH
V_ID
V_IL
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V_ID = 600 mV.
V_IH = V_ref + 250 mV (AC voltage levels) for differential inputs. V_IH = V_DD for LVCMOS inputs.
V_IL = V_ref − 250 mV (AC voltage levels) for differential inputs. V_IL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; pulse duration
SSTUG32868_1
Product data sheet
Rev. 01 — 23 April 2007
© NXP B.V. 2007. All rights reserved.
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