SC16C852V_08 Datasheet, PDF (8/54 Pages) NXP Semiconductors – 1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface

NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table 2. Pin description …continued
Symbol Pin
Type Description
TFBGA36 HVQFN48
RTSA
C6
RTSB
E5
33
O Request to Send (active LOW). These outputs are associated with individual
22
O ^{UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter}
has data ready and waiting to send. Writing a logic 1 in the modem control
register MCR[1] will set this pin to a logic 0, indicating data is available. After a
reset this pin will be set to a logic 1.
RXA
D1
5
RXB
C2
4
I
Receive data A, B. These inputs are associated with individual serial channel
I
data to the SC16C852V receive input circuits, A through B. The RX signal will
be a logic 1 during reset, idle (no data), or when not receiving data. During the
local Loopback mode, the RX input pin is disabled and TX data is connected to
the UART RX input, internally.
RXRDYA -
RXRDYB -
31
O Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR
18
O ^{status for individual receive channels (A to B). RXRDYn is primarily intended}
for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0
indicates there is a receive data to read/upload, that is, receive ready status
with one or more RX characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed trigger level has not
been reached. This signal can also be used for single mode transfers (DMA
mode 0).
TXA
D2
7
TXB
E1
8
O Transmit data A, B. These outputs are associated with individual serial
O ^{transmit channel data from the SC16C852V. The TX signal will be a logic 1}
during reset, idle (no data), or when the transmitter is disabled. During the local
Loopback mode, the TX output pin is disabled and TX data is internally
connected to the UART RX input.
TXRDYA -
TXRDYB -
43
O Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR
6
O ^{status for individual transmit channels (A to B). TXRDYn is primarily intended}
for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual
channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is,
at lease one location is empty and available in the FIFO or THR. This pin goes
to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO
or THR. This signal can also be used for single mode transfers (DMA mode 0).
V_DD
C4
V_SS
D4
XTAL1 D3
42
I
Power supply input.
17^[1]
I
Signal and power ground.
13
I
Crystal or external clock input. Functions as a crystal input or as an external
clock input. A crystal can be connected between this pin and XTAL2 to form an
internal oscillator circuit. Alternatively, an external clock can be connected to
this pin to provide custom data rates (see Section 6.9 “Programmable baud
rate generator”). See Figure 7.
XTAL2 F2
14
O Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal
oscillator output or buffered clock output. Should be left open if an external
clock is connected to XTAL1.
[1] HVQFN48 package die supply ground is connected to both V_SS pin and exposed center pad. V_SS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
SC16C852V_4
Product data sheet
Rev. 04 — 14 January 2008
© NXP B.V. 2008. All rights reserved.
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