PSMN7R0-30YL Datasheet, PDF (8/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN7R0-30YL
N-channel TrenchMOS logic level FET
16
R_DSon
(mΩ)
14
12
10
8
6
4
0
003aac722
3.2
V_GS (V) = 4.5
10
20
40
60
80 _{ID (A)} 100
V_DS
I_D
V_GS(pl)
V_GS(th)
V_GS
Q_GS1 Q_GS2
Q_GS
Q_GD
Q_G(tot)
003aaa508
Fig 14. Gate charge waveform definitions
Fig 13. Drain-source on-state resistance as a function
of drain current; typical values
10
V_GS
(V)
8
V_DS = 12 (V)
003aac725
6
V_DS = 19 (V)
4
2
0
0
5
10
15
20
25
Q_G (nC)
1600
C
(pF)
1200
800
400
C_iss
C_oss
C_rss
0
10^-1
1
003aac723
10
V_DS (V) ¹⁰²
Fig 15. Gate-source voltage as a function of gate
charge; typical values
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN7R0-30YL_1
Preliminary data sheet
Rev. 01 — 15 October 2008
© NXP B.V. 2008. All rights reserved.
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