PSMN7R0-30YL Datasheet, PDF (7/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN7R0-30YL
N-channel TrenchMOS logic level FET
2500
C
(pF)
C_iss
2000
1500
C_rss
003aac724
1000
500
0
0
2
4
6
8
10
V_GS (V)
3
V_GS(th)
(V)
2
1.5
1
0.5
0
-60
max
typ
min
003aab272
0
60
120
180
T_j (°C)
Fig 9. Input and reverse transfer capacitances as a
Fig 10. Gate-source threshold voltage as a function of
function of gate-source voltage; typical values
junction temperature
10^−3
I_D
(A)
10^−4
003aab271
2
a
1.6
min typ
max
1.2
003aab273
0.8
10^−5
0.4
10^−6
0
0.5
1
1.5
2
2.5
V_GS (V)
0
-60
0
60
120
180
T_j (°C)
Fig 11. Sub-threshold drain current as a function of
gate-source voltage
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN7R0-30YL_1
Preliminary data sheet
Rev. 01 — 15 October 2008
© NXP B.V. 2008. All rights reserved.
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