MFRC522_10 Datasheet, PDF (8/96 Pages) NXP Semiconductors – Contactless reader IC

NXP Semiconductors
MFRC522
Contactless reader IC
ISO/IEC 14443 A framing at 106 kBd
start
8-bit data
start bit is 1
odd
parity
8-bit data
odd
parity
8-bit data
odd
parity
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
start
start bit is 0
burst of 32
subcarrier clocks
8-bit data
odd
parity
8-bit data
Fig 6. Data coding and framing according to ISO/IEC 14443 A
odd
parity
8-bit data
even
parity
even parity at the
end of the frame
001aak585
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally according to the transfer speed. Automatic
parity generation can be switched off using the MfRxReg register’s ParityDisable bit.
8.1 Digital interfaces
8.1.1 Automatic microcontroller interface detection
The MFRC522 supports direct interfacing of hosts using SPI, I²C-bus or serial UART
interfaces. The MFRC522 resets its interface and checks the current host interface type
automatically after performing a power-on or hard reset. The MFRC522 identifies the host
interface by sensing the logic levels on the control pins after the reset phase. This is done
using a combination of fixed pin connections. Table 5 shows the different connection
configurations.
Table 5.
Pin
SDA
I2C
EA
D7
D6
D5
D4
D3
D2
D1
Connection protocol for detecting different interface types
Interface type
UART (input)
SPI (output)
I²C-bus (I/O)
RX
NSS
SDA
0
0
1
0
1
EA
TX
MISO
SCL
MX
MOSI
ADR_0
DTRQ
SCK
ADR_1
-
-
ADR_2
-
-
ADR_3
-
-
ADR_4
-
-
ADR_5
MFRC522_34
Product data sheet
PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 5 March 2010
112134
© NXP B.V. 2010. All rights reserved.
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