MFRC522_10 Datasheet, PDF (25/96 Pages) NXP Semiconductors – Contactless reader IC

NXP Semiconductors
MFRC522
Contactless reader IC
8.2.3 Serial data switch
Two main blocks are implemented in the MFRC522. The digital block comprises the state
machines, encoder/decoder logic. The analog block comprises the modulator and
antenna drivers, the receiver and amplifiers. It is possible for the interface between these
two blocks to be configured so that the interfacing signals are routed to pins MFIN and
MFOUT.
This topology allows the analog block of the MFRC522 to be connected to the digital block
of another device.
The serial signal switch is controlled by the TxSelReg and RxSelReg registers.
Figure 20 shows the serial data switch for p-driver TX1 and TX2.
INTERNAL
CODER
MFIN
DriverSel[1:0]
3-state 00
INVERT IF envelope
InvMod = 1
01
10
1 11
INVERT IF
PolMFin = 0
to driver TX1 and TX2
0 = impedance = modulated
1 = impedance = CW
001aak593
Fig 20. Serial data switch for p-driver TX1 and TX2
8.2.4 MFIN and MFOUT interface support
The MFRC522 is divided into a digital circuit block and an analog circuit block. The digital
block contains state machines, encoder and decoder logic and so on. The analog block
contains the modulator and antenna drivers, receiver and amplifiers. The interface
between these two blocks can be configured so that the interfacing signals can be routed
to pins MFIN and MFOUT; see Figure 21 on page 26. This configuration is implemented
using TxSelReg register’s MFOutSel[3:0] and DriverSel[1:0] bits and RxSelReg register’s
UARTSel[1:0] bits.
This topology allows some parts of the analog block to be connected to the digital block of
another device.
Switch MFOutSel in the TxSelReg register can be used to measure MIFARE and
ISO/IEC14443 A related signals. This is especially important during the design-in phase
or for test purposes as it enables checking of the transmitted and received data.
The most important use of pins MFIN and MFOUT is found in the active antenna concept.
An external active antenna circuit can be connected to the MFRC522’s digital block.
Switch MFOutSel must be configured so that the internal Miller encoded signal is sent to
pin MFOUT (MFOutSel = 100b). UARTSel[1:0] must be configured to receive a
Manchester signal with subcarrier from pin MFIN (UARTSel[1:0] = 01).
It is possible to connect a passive antenna to pins TX1, TX2 and RX (using the
appropriate filter and matching circuit) and an active antenna to pins MFOUT and MFIN at
the same time. In this configuration, two RF circuits can be driven (one after another) by a
single host processor.
MFRC522_34
Product data sheet
PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 5 March 2010
112134
© NXP B.V. 2010. All rights reserved.
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