MFRC522_10 Datasheet, PDF (29/96 Pages) NXP Semiconductors – Contactless reader IC

NXP Semiconductors
MFRC522
Contactless reader IC
The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
Table 18. Interrupt sources
Interrupt flag Interrupt source
TimerIRq
timer unit
TxIRq
transmitter
CRCIRq
CRC coprocessor
RxIRq
receiver
IdleIRq
ComIrqReg register
HiAlertIRq
FIFO buffer
LoAlertIRq
FIFO buffer
ErrIRq
contactless UART
Trigger action
the timer counts from 1 to 0
a transmitted data stream ends
all data from the FIFO buffer has been processed
a received data stream ends
command execution finishes
the FIFO buffer is almost full
the FIFO buffer is almost empty
an error is detected
8.5 Timer unit
The MFRC522A has a timer unit which the external host can use to manage timing tasks.
The timer unit can be used in one of the following timer/counter configurations:
• Timeout counter
• Watchdog counter
• Stop watch
• Programmable one shot
• Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event occurred after a specific time. The timer can be triggered by events
explained in the paragraphs below. The timer does not influence any internal events, for
example, a time-out during data reception does not automatically influence the reception
process. Furthermore, several timer-related bits can be used to generate an interrupt.
The timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal
oscillator. The timer consists of two stages: prescaler and counter.
The prescaler (TPrescaler) is a 12-bit counter. The reload values (TReloadVal_Hi[7:0] and
TReloadVal_Lo[7:0]) for TPrescaler can be set between 0 and 4095 in the TModeReg
register’s TPrescaler_Hi[3:0] bits and TPrescalerReg register’s TPrescaler_Lo[7:0] bits.
The reload value for the counter is defined by 16 bits between 0 and 65535 in the
TReloadReg register.
The current value of the timer is indicated in the TCounterValReg register.
When the counter reaches 0, an interrupt is automatically generated, indicated by the
ComIrqReg register’s TimerIRq bit setting. If enabled, this event can be indicated on
pin IRQ. The TimerIRq bit can be set and reset by the host. Depending on the
configuration, the timer will stop at 0 or restart with the value set in the TReloadReg
register.
The timer status is indicated by the Status1Reg register’s TRunning bit.
MFRC522_34
Product data sheet
PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 5 March 2010
112134
© NXP B.V. 2010. All rights reserved.
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