LPC2109_11 Datasheet, PDF (8/46 Pages) NXP Semiconductors – Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN

NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
Table 3. Pin description …continued
Symbol
Pin
Type Description
P1[16]/
16
TRACEPKT0
O Trace Packet, bit 0. Standard I/O port with internal pull-up.
P1[17]/
12
TRACEPKT1
O Trace Packet, bit 1. Standard I/O port with internal pull-up.
P1[18]/
8
TRACEPKT2
O Trace Packet, bit 2. Standard I/O port with internal pull-up.
P1[19]/
4
TRACEPKT3
O Trace Packet, bit 3. Standard I/O port with internal pull-up.
P1[20]/
48
TRACESYNC
O Trace Synchronization. Standard I/O port with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to operate as
Trace port after reset.
P1[21]/
44
PIPESTAT0
O Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1[22]/
40
PIPESTAT1
O Pipeline Status, bit 1. Standard I/O port with internal pull-up.
P1[23]/
36
PIPESTAT2
O Pipeline Status, bit 2. Standard I/O port with internal pull-up.
P1[24]/
32
TRACECLK
O Trace Clock. Standard I/O port with internal pull-up.
P1[25]/EXTIN0 28
I
External Trigger Input. Standard I/O with internal pull-up.
P1[26]/RTCK
24
I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger
synchronization when processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as
Debug port after reset.
P1[27]/TDO
64
O Test Data out for JTAG interface.
P1[28]/TDI
60
I
Test Data in for JTAG interface.
P1[29]/TCK
56
I
Test Clock for JTAG interface. This clock must be slower than ¹â„₆ of the CPU clock
(CCLK) for the JTAG interface to operate.
P1[30]/TMS
52
I
Test Mode Select for JTAG interface.
P1[31]/TRST
20
I
Test Reset for JTAG interface.
TD1
10
O CAN1 transmitter output.
RESET
57
I
External reset input; a LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1
62
I
Input to the oscillator circuit and internal clock generator circuits.
XTAL2
61
O Output from the oscillator amplifier.
V_SS
6, 18, 25, I
Ground: 0 V reference.
42, 50
V_SSA
59
I
Analog ground; 0 V reference. This should nominally be the same voltage as V_SS,
but should be isolated to minimize noise and error.
V_SSA(PLL)
V_DD(1V8)
58
I
PLL analog ground; 0 V reference. This should nominally be the same voltage as
V_SS, but should be isolated to minimize noise and error.
17, 49
I
1.8 V core power supply; this is the power supply voltage for internal circuitry.
LPC2109_2119_2129
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2011
© NXP B.V. 2011. All rights reserved.
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